1. Field of Invention
The invention relates to a system and method of high speed clock/data recovery, and in particular to a system and method of oversampling high speed clock/data recovery.
2. Related Art
In the network communication, the trend of research and development relating to the bandwidth used for data transmission is toward the development of the Serial Link Technology of high speed and low cost, and in particular for use in high speed data transmission. In this connection, the oversampling technology is widely utilized. In this technology, multiple clock phases are used to oversample the high speed data, and then the high speed clock and data are recovered through the information of the phase of data transition.
With regard to the prior art, a technology is disclosed in the US patent publication No. 20030142773, wherein the rising and falling edges of the clock are utilized to detect and determine if the recovered clock phase needs to be updated. In each clock period, the clock is updated as soon as a clock phase change occurs. In addition, in the US publication patent No 20040022339 an oversampling circuit is disclosed to reduce the frequency of the output signals.
In practice, the difficulties encountered by the high speed data recovery circuit is that, the data must be accurately processed within the short clock period (usually a few nanoseconds). However, the technology disclosed by any of the prior cases does not provide a practical and satisfactory solution to this problem.